An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
As stated, SRAM devices are one form of RAM device. SRAM devices differ from DRAM devices in that they do not require constant refreshing. A standard SRAM cell 100 is shown in FIG. 1A. Cell 100 consists of four transistors 106, 108, 110, 112, and two control transistors 102 and 104. Data is stored with either a high potential at node A and a low potential at node B, or a low potential at node A and a high potential at node B. This means that two stable states are available which are defined as a logic “1” or a logic “0”.
In FIG. 1A, the logic state of SRAM cell 100, i.e., either a “1” or “0”, is read by sensing the cell current on bit line pair comprised of bit lines 116 and 117 and/or the differential voltage developed thereon. When word line 118 is selected, cell 100 is activated by turning on control transistors 102 and 104. If the activated SRAM cell 100 is in logic state “1” node A is high and node B is low. Transistor 108 will be off, transistor 112 will be on, transistor 106 will be on, and transistor 110 will be off. Since transistors 112 and 104 are on, bit line 117 will carry cell current, while bit line 116 will not carry any cell current since transistor 108 is off.
The logic state “0” would be the opposite with node A low and node B high. Transistor 108 will be on, transistor 112 will be off, transistor 106 will be off, and transistor 110 will be on. Bit line 116 will carry cell current, while bit line 117 will not carry cell current.
FIG. 1B illustrates an alternative SRAM cell 150 as contained in the prior art. In this cell 150, transistors 206 and 210 are replaced by two resistors 252, 254. The operation of the cell 150, however, is essentially the same as the operation of the cell 100 (FIG. 1A). The SRAM cell 150 can also be used in and accessed from the memory and SRAM devices illustrated and described below in FIGS. 2 and 3.
Thus, FIGS. 1A and 1B illustrate conventional SRAM devices. If the SRAM cell is perfectly symmetrical then upon start-up or power supply voltage, Vdd, being applied the two output nodes, V1 and V2, both go to the same potential 1.25V. In reality of course the cell can never be perfectly symmetrical and random variations in parameters will cause it to start in some random configuration with either a “one” or “zero” stored in the cell.
These conventional SRAM cells can be fabricated with a built in asymmetry by making some devices with a threshold voltage, VT, larger than normal, and some devices normal by controlling the doping content of the devices. This can also be conventionally done by making some of the devices, e.g. transistors, larger than others. These approaches, however, add cost and complexity to the fabrication process.
Other alternative approaches for providing such built in asymmetry are described in U.S. Pat. No. 6,141,248, entitled “DRAM AND SRAM MEMORY CELLS WITH REPRESSED MEMORY,” by L. Forbes, and A. R. Reinberg, issued Oct. 31, 2000; and U.S. Pat. No. 6,141,238, entitled “DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS WITH REPRESSED FERROELECTRIC MEMORY METHODS OF READING SAME, AND APPARATUSES INCLUDING SAME,” by L. Forbes, K. Y. Ahn, W. P. Noble and A. R. Reinberg, issued Oct. 31, 2000.
When the SRAM cells are programmed in this manner upon start-up and/or when power supply voltage is first applied to the cell it will always start in one preferred state with either a logic state “0” or a logic state “1” stored in the cell. The use of the SRAM cells programmed in this manner, where it can also be used as a PROM, would be useful in either embedded or stand alone SRAM. The cells can operate either as RAM or ROM, and could also be used as field or inservice programmable read only memories or electrically alterable programmable read only memories (EAPROM or EEPROM).
These products provide system level integration solutions for high volume applications that incorporate logic, memory and megacells system building blocks. Gate arrays and embedded arrays can combine over a million gates of logic, with SRAM, ROM, EEPROM and flash memories into a single chip. Memory blocks of volatile and non-volatile memory technology lets you integrate, on-chip: ROM, Flash, EEPROM and SRAM. Memory Compilers enable you to generate, to your exact specifications: SRAM (single-port, dual-port or FIFO) memory functions.
As before, a drawback to the above approaches is that they add cost and complexity to the fabrication process. Also, in conjunction with using floating gate transistors within the memory cells, there are additional problems to resolve. The following description for programming floating gate transistors explains some of these problems.
In order to enable a reasonable write speed the floating gate transistor uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, result in slow write and erase speeds even at very high electric fields. The combination of very high electric fields and damage by hot electron collisions in the oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase.
Approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function, the use of structured surfaces which increase the localized electric fields, and amorphous SiC gate insulators with larger electron affinity, χ, to increase the tunneling probability and reduce erase time.
However, all of these approaches relate to increasing tunneling between the floating gate and the substrate such as is employed in a conventional ETOX device and do not involve tunneling between the control gate and floating gate through and inter-poly dielectric.
The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interpoly dielectric insulator for erase. (See generally, F. Masuoka et al., “A new flash EEPROM cell using triple polysilicon technology,” IEEE Int. Electron Devices Meeting, San Francisco, pp. 464-67, 1984; F. Masuoka et al., “256K flash EEPROM using triple polysilicon technology,” IEEE Solid-State Circuits Conf., Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxide and silicon nitride were tried. (See generally, S. Mori et al., “reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. On VLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.
Therefore, there is a need in the art to provide improved SRAM cells for memory devices with a definitive asymmetry so that the cell always starts in a particular state. In this manner, the cell can be used both stand alone SRAM and for embedded SRAM in combination with a microcontroller. Any such SRAM cells which employ a floating gate transistor which can be programmed to provide the SRAM cell with a definitive asymmetry should avoid the added cost, size and complexity described above and should avoid the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. Likewise, the floating gate transistors need to avoid the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, when using an interpoly dielectric insulator erase approach for the non-volatile component, the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems must be avoided.